In traditional data communications systems, data which is transmitted or received in packet data mode networks, such as integrated services digital network (ISDN), is enclosed by unique delimiters. These delimiters, known as flags, are represented by a digital sequence of "01111110". This data stream includes a Control/Address field (CAF), a Data Field (DF) and an error checking field such as a Cyclic Redundancy Check (CRC).
To maintain uniqueness of these delimiters all three fields are "zero inserted". This means that after any five consecutive ones, a zero is inserted between the 5th one and the adjacent data bit.
During a transmission sequence, the CRC field data is based on a division of the CAF and DF fields by a known polynomial. The remainder from that division is appended to the CAF and DF fields. During a receiving sequence, the division by the polynomial is again performed on the CAF and DF. The result is compared to the incoming CRC field. If the two calculations yield consistent and correct results the information in the CAF and DF fields is accepted, otherwise it is rejected.
In traditional PDM systems such as ISDN, a message is the combination of a CAF field plus the DF field. These message lengths can vary from 4 bytes to 260 bytes. The user must allocate a block of memory that can accommodate the largest possible message even though only a small amount of that block may be used, such as for a 4 byte message.
In traditional systems, variable length blocks and variable starting addresses are typically not used because of the software housekeeping and overall overhead introduced to the central processing unit (CPU). The traditional approach is to reserve the CPU to process the incoming and outgoing messages and to program the DMA and the HDLC controller. Allocated blocks are always equal to or greater than the largest message. A single message occupies each block starting at the top of each block. Because ISDN allows messages as long as 260 bytes a memory space of 256 bytes (2.sup.8)is too small. Unfortunately, because of binary arithmetic, in this case the user will have to allot a memory space of 512 bytes (2.sup.9) to accommodate a 260 byte message.
FIG. 1 shows a conceptualized block diagram view of a traditional HDLC system used for LAPD. (LAPD is a protocol used in ISDN and stands for "link access protocol in the "D" channel"). The purpose of such a system is to communicate with other systems through a packet data network, using a common protocol such as LAPD, LAPB, or X.25.
A transceiver 110 is coupled to receive and transmit packet data from a twisted pair "S" or "U" interface 112. This twisted pair interface 112 might be for example an existing telephone line.
The transceiver 110 is also coupled to an HDLC controller 114 over a serial digital data bus 116. The HDLC controller includes a receiver circuit RX 118, a transmitter circuit TX 120 and a FIFO buffer 122. The HDLC controller 114 is coupled to a DMA controller 124 through a parallel digital data bus 126.
The DMA controller 124 is coupled to a central processing unit (CPU) 128 and a memory management unit (MMU) 130 through the CPU bus 132. The MMU 130 is coupled to the memory 134 through the memory bus 136.
Each of the transceiver 110, the HDLC controller 114, the DMA controller 124, the CPU 128 and the MMU 130 are coupled to receive from and transmit to a communication/control signal bus 138. The MMU 130 and the memory 134 have a separate communication/control signal bus 140. The HDLC controller 114 is coupled to supply an interrupt signal 142 to the CPU 128, a buffer full signal (RBF) 144 to the DMA controller 124 and a buffer empty signal (BES) 146 to the DMA controller 124. The DMA controller 124 is coupled to supply an interrupt signal 148 to the CPU 128.
In FIG. 1 the twisted pair interface 112, the transceiver 110, the serial digital data bus 116 and the HDLC controller 114 form the packet data mode (PDM) system. The DMA controller 124, the CPU bus 132, the CPU 128, the MMU 130 the memory bus 136 and the memory 134 form the digital processing system. The parallel digital data bus 126 couples the PDM system to the digital processing system.
The roles of the individual blocks within the system of FIG. 1 are described below: